Monday, July 7, 2008

More on Moore's Law

Thanks to an article called "Intel's Gelsinger Sees Clear Path To 10nm Chips", I revisited my post, Moore's Wall.

The article (and comments) said that Intel's current state-of-the-art 45nm process will be followed by a 32nm process starting next year, then 22nm in 2011, 16nm in 2013, and around 11nm in 2015. A couple of years after that, Intel will be sub-10nm.

(Serious technology geeks should read THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2007. The list of Grand Challenges needed to maintain the pace of Moore's Law is impressive. Of necessity, the report was obsolete by the time it was published.)

I'd like to add my own two cents worth.

There are some serious fundamental limits to the increased reduction in component size. For example, the capacitor that stores charge in a DRAM memory cell contains only about 70 electrons (this statistic may now be obsolete--it was accurate at one time). Fractional electrons are not available, and some significant number of electrons is required for reliability (you refresh a DRAM cell before it loses too many electrons (to leakage) to be certain of its state). Also, some implementations record multiple bits per capacitor (4 levels stores 2 bits, 8 levels stores 3 bits, etc.), placing stricter limits on accuracy.

Another serious limitation is that as the components shrink, a single hit by ionizing radiation (whether gamma, alpha, proton, or beta) can completely overwhelm the state. These occur naturally from trace radioactive components in the substrate, packaging, and environment. Today, we use Error Correcting Codes to allow for and correct these natural transitional errors, at the cost of requiring an ever-increasing share of our memory to be used as redundant ECC memory. You don't even notice that a hard drive contains a significant percentage of redundant information, allowing the reliable recovery of data from a medium guaranteed to have defects.

This last problem has an interesting solution. Error correcting codes provide some number of additional bits to identify the errors and produce an accurate result. Some day, I predict that the logic circuitry itself will also incorporate ECC. This means that a simple "adder", a logic array that adds two integers together, will no longer have just the logic needed to perform the addition, but a significant amount of additional logic to perform a simultaneous ECC for the entire operation. A complex ECC logic could perform more reliably than even triplicated logic, with less redundancy.

Your cell phone today uses an impressive degree of ECC (called something else) to extract a reliable signal from an extremely noisy environment which includes many other transmitters all vying for the same pieces of the electromagnetic spectrum. The ECC technology is sufficiently advanced that a signal can reliably extracted even when the noise level exceeds the signal level.

Some day, the logic circuits that operate your computers may have a similar design: while no one component is reliable from one microsecond to the next, the net effect of the system as a whole will still be an incredibly dependable result. Worded another way, the memory cell or logic gate that today is reliably on or off, may tomorrow be "well, it's sometimes right, at least 25% of the time" and a network of related and redundant ECC logic will save the day.

Puts a whole new meaning to the term "fuzzy logic".

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